1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device, which can accomplish the selective silicidation of a desired region on a semiconductor substrate.
2. Description of the Related Art
As a semiconductor device has been developed to have a high degree of integration, patterns formed on a chip become smaller in size and the gap between the patterns becomes narrower. In the past, polysilicon has been a very useful material as a wiring material such as a gate electrode or a bit line. However, as patterns are gradually smaller, the resistivity of the polysilicon becomes higher, resulting in increasing RC time delays and IR voltage drops. In order to improve short channel and punchthrough effects caused by a decrease of a gate length of the transistor, the junction depths of source/drain regions should be thinner while parasitic resistances of the source/drain regions, e.g., a sheet resistance and a contact resistance, need to be reduced.
Accordingly, a self-aligned silicide (hereinafter, referred to as a salicide) process of forming silicides on the surface of the gate region and the source/drain regions is used as a new metalization process capable of reducing the resistivity of the gate electrode and the parasitic resistances of the source/drain regions. The salicide process selectively forms the silicides only on the gate electrode and the source/drain regions. The silicide is formed by using a material such as titanium silicide (TiSi2) or the group-VIII silicides such as PtSi2, PdSi2, CoSi2 and NiSi2. In the semiconductor device having a design rule of about 0.25 μm, it is preferred to use the cobalt silicide of which the dependence to a critical dimension of the gate is low. It is known that the cobalt silicide has a low resistivity of 16˜18 μΩ-cm and a stable characteristic at high temperatures of about 900 Celsius Degrees.
In case of a logic device using the cobalt silicide as the material of the gate electrode, the silicide formation is excluded in an analog region since the gate is used as the resistance element in the analog region. Accordingly, in order to selectively form the silicide on the desired region, before a metal layer for silicide is deposited, there is formed a silicidation blocking layer (SBL) consisting of a material that is not reactive to the metal layer.
FIGS. 1A to 1C are sectional views illustrating a conventional method of manufacturing a logic device having the silicidation blocking layer.
Referring to FIG. 1A, a field oxide layer 11 is formed on a semiconductor substrate 10 by a conventional shallow trench isolation process, thereby defining an active region 12 on the substrate 10. Next, after a gate oxide layer 14 is formed on the active region 12 of the substrate 10, a polysilicon layer is deposited on the gate oxide layer 14. The polysilicon layer is doped with a high concentrated N-typed dopant by a doping process, e.g., POCL3 diffusion, ion implantation, or in-situ doping. Then, the polysilicon layer is patterned by a photolithography process to form N+ typed gate electrodes 16.
After an insulation material such as silicon oxide or silicon nitride is deposited on the gate electrodes 16 and the substrate 10 by a chemical vapor deposition (CVD) process, the insulation layer is anisotropically etched away to form gate spacers 18 on the sidewalls of the gate electrodes 16. Then, source and drain regions are formed in the surface of the substrate on both sides of the gate electrode 16 by an ion implantation process. As a result of the above-described process, MOS transistors including the gate electrode 16 and the source/drain regions are completed.
Next, an oxide is deposited at a temperature of about 750 Celsius Degrees on the MOS transistors and the substrate 10 by a CVD process to form a buffer layer 20 having a thickness of about 50˜100 Å. Silicon nitride is deposited at the temperature of about 670 Celsius Degrees on the buffer layer 20 by a low pressure chemical vapor deposition (LPCVD) process to form a silicidation blocking layer 22 having a thickness of about 100˜200 Å. The buffer layer 20 prevents an attack of the silicon substrate 10 and the field oxide layer 11 located thereunder during a subsequent etching process of the silicidation blocking layer 22.
Referring to FIG. 1B, a photoresist pattern 24 is formed on the silicidation blocking layer 22 by a photo process, to thereby expose a region where silicide is to be formed. Then, the silicidation blocking layer 22 in the region in which the silicide is to be formed is dry-etched by using the photoresist pattern 24 as a mask. As a result, there is formed the silicidation blocking layer pattern (hereinafter, referred to as a SBL pattern) 22a defining an activation region and a non-activation region of the silicidation.
Referring to FIG. 1C, the photoresist pattern 24 is removed by ashing and stripping processes. Next, a wafer is put in a chamber of RF sputtering equipment after a typical wet cleaning process is performed to remove particles, metal impurities, organic contaminants or a native oxide created on surfaces of the silicon layer and the polysilicon layer.
Then, after a RF plasma etching is carried out in order to remove the native oxide to be re-created during movement of the wafer, a cobalt layer is in-situ deposited on the wafer by a sputtering process. A rapid thermal annealing or a heat treatment using a furnace is performed twice to form the cobalt suicides 26 only in the exposed gate region and/or active region. At that time, no silicide is formed in the gate region and/or the active region covered by the SBL pattern 22a. 
According to the conventional method, since the silicidation blocking layer is deposited after the gate and the source/drain regions are formed, a heat budget at 750 Celsius Degrees/670 Celsius Degrees causes the impurities doped in the gate and the source/drain regions to be diffused and redistributed. As a result, a short channel effect such as a punch-through between the source/drain regions is generated or the impurities in the gate electrode penetrate through the gate oxide into the channel region.